1. Field of the Invention
The present invention relates to a solid imaging device which operates by a novel driving method.
2. Description of the Related Art
Conventional amplification type solid imaging devices have been proposed which include a pixel section, including pixels each having an amplification function, and scanning circuitry provided in the periphery of the pixel section for reading pixel data. In particular, APS (active pixel sensor type) image sensors are known as amplification-type solid imaging devices in which pixel structures are constructed from CMOS elements, which facilitates integration with peripheral driving circuitry and signal processing circuitry.
In accordance with an APS image sensor structure, it is necessary to provide a photoelectric conversion section, an amplification section, a pixel selection section, and a reset section within one pixel. Furthermore, an APS image sensor includes 3 or 4 MOS transistors (T) in addition to the number of photodiodes (PD) usually composing the photoelectric conversion section.
FIG. 7 shows the structure of an APS image sensor of a “PD+4T” structure, incorporating one photodiode (PD) and four MOS transistors. A “PD+4T” structure is disclosed in R. M. Guidash et al., IEDM Tech. Digest, p. 927(1997).
Each pixel in the APS image sensor shown in FIG. 7 includes a photodiode (PD) 1, and four transistors, i.e., a transfer gate transistor 2, a reset gate transistor 3, an amplification transistor 4, and a pixel selection transistor 5.
A charge transfer clock line 12, a reset clock line 13, and a pixel selection clock line 15 supply driving pulse voltages, i.e., VTX, VRS, and VSE, respectively, along the horizontal direction. The charge transfer clock line 12, the reset clock line 13, and the pixel selection clock line 15 are coupled to vertical scanning circuits 23, 22, and 21, respectively. Driving pulse voltages VRS(i), VSE(i), and VTX(i) for an ith row are applied to the gate of the reset gate transistor 3, the gate of the pixel selection transistor 5, and the gate of the transfer gate transistor 2, respectively.
A power line 14 and a vertical signal line 16 are provided for respective pixels along the vertical direction as shown in FIG. 7. A load transistor 17 is coupled to the vertical signal line 16 for each column of pixels. A signal on the vertical signal line 16 is transmitted to a horizontal signal line 36 via a driving transistor 31 and a horizontal selection switching transistor 32.
The horizontal selection switching transistor 32 is driven by a horizontal scanning signal 35 provided from a horizontal scanning circuit 34. A load transistor 33 is coupled to the horizontal signal line 36. A signal on the horizontal signal line 36 is amplified by a buffer amplifier 37 so as to be output as an output signal OS. Reference numeral VD represents a constant voltage supply power.
FIG. 8 is a timing diagram illustrating the circuit operation of the “PD+4T” structure shown in FIG. 7.
Driving pulse voltages VRS(i), VSE(i), and VTX(i) for an ith row and driving pulse voltages VRS(i+1), VSE(i+1), and VTX(i+1) for an i+1th row have respectively similar waveforms but are one horizontal scanning period (1H) apart from one another. The following description will be directed to the ith row.
During a period t1, the reset gate transistor 3 (RS(i)) is turned ON. Since this causes a decrease in the gate potential energy, the charge shifts from a charge detection node FD (FIG. 7) to the drain of the reset gate transistor 3 (RS(i)). As a result, the potential of the charge detection node FD is reset to a supply voltage VD.
During a period t2, the reset gate transistor 3 (RS(i)) is turned OFF, but the charge detection node FD is maintained at the potential VD, which existed at the time of resetting.
During a period t3, the transfer gate transistor 2 (TX(i)) is turned ON. Since this causes a decrease in the gate potential energy, the signal charge which is stored in the photodiode 1 (PD) is transferred to the charge detection node FD.
During a period t4, the transfer gate transistor 2 (TX(i)) is turned OFF, but the charge detection node FD is maintained at the potential which existed at the time of signal charge transfer.
During a period t6, the transfer gate transistor 2 (TX(i)) and the reset gate transistor 3 (RS(i)) are both turned ON. Since this causes a decrease in the gate potential energy in both transistors 2 and 3, the charge shifts from the photodiode 1 (PD) and the charge detection node FD to the drain of the reset gate transistor 3 (RS(i)). As a result, the potential of the photodiode 1 (PD) is reset to a potential (Fk) which is dependent on a transfer gate transistor high level (described later), and the potential of the charge detection node FD is reset to the supply voltage VD.
During a period t7, the transfer gate transistor 2 (TX(i)) is turned OFF, so as to isolate the photodiode 1 (PD) from external circuitry. The period t7 is a preliminary period for isolating the charge detection node FD, as well as the photodiode 1 (PD), from external circuitry after fixing the potential of the photodiode 1 (PD) at the potential (Fk) which is dependent on the transfer gate transistor high level.
During the periods t1 to t4, the driving pulse voltage (VSE(i)) on the pixel selection clock line 15 is applied to the gate of the pixel selection transistor 5, whereby the pixel selection transistor 5 is turned ON. Therefore, a detection signal obtained at the charge detection node FD during the periods t1 to t4 is output to the vertical signal line 16.
The circuit operation during the periods t1 to t7 occurs during a horizontal blanking period H-BLK. The reset signal and the detection signal appear on the vertical signal line 16 during the periods t2 and t4, respectively. Therefore, a net signal value can be obtained by calculating a difference between the signal levels during the period t2 and the period t4 through a subsequently-performed correlated double sampling (CDS) process. These signals are sequentially read by the horizontal scanning circuit 34 during a horizontal effective period (H-EFF).
The circuit structure shown in FIG. 7 and the circuit operation shown in FIG. 8 may experience the following problems when the charge is transferred from the photodiode 1 (PD) to the charge detection node FD.
FIG. 9 shows potential energies appearing at the photodiode 1 (PD(i)), transfer gate transistor 2 (TX(i)), and the reset gate transistor 3 (RS(i)). The circuit operation illustrated in FIG. 9 is now described with reference to the timing diagram of FIG. 8.
After the charge detection node FD is reset to the supply voltage VD during the period t1 (FIG. 8), the amount of signal charge stored in the photodiode 1 (PD(i)) is read during the period t3. The amount of signal charge read at this time, which in theory would correspond to the difference between a signal level potential energy Fs and a high level potential energy F0 of the transfer gate transistor 2 (TX(i)) in an ON state (i.e., Fs−F0), is actually greater than that by Δ1 (i.e., Fs−F1). This is because excess charge is released from the photodiode 1 (PD(i)) in a floating state, beyond a potential energy barrier Δ1, due to thermal release effects.
This phenomenon occurs after every signal read operation. As a relatively “dark” signal state (i.e., a signal state under no light irradiation) continues over several read periods after a relatively “bright” signal state (i.e., a signal state under incident light), the potential energy level of the photodiode 1 (PD(i)) after each read operation becomes gradually deeper, e.g., Δ2, Δ3, and Δ4. This indicates that a low level signal is being output even during a dark signal state. When a bright signal state occurs again, the signal charge will be stored but only from a deep potential level, resulting in a corresponding decrease in the final signal charge level.
Therefore, the signal charge amount experiences a decrease when a dark signal state is followed by a bright signal state, whereas an extra signal charge amount is output when a bright signal state is followed by a dark signal state. In other words, a so-called residual image phenomenon occurs in the circuit structure shown in FIG. 7 and the circuit operation shown in FIG. 8.
The reset gate transistor 3 (RS(i)) shown in FIG. 9 is of an embedded channel type, and has a deeper potential energy than that of the transfer gate transistor 2 (TX(i)).
It is known in the art that the residual image phenomenon can be effectively controlled by introducing a bias charge. For example, a BBD (bucket brigade device) which essentially repeats operations similar to those above, can be used to introduce a constant bias charge other than the signal charge. In the case of a photodiode incorporated in an image sensor, bias charge may be introduced by providing bias light. However, provision of bias light will impose a substantial burden on the actual use of the device and result in an increase in photoelectric conversion noise.
Another method has been proposed which involves separately providing a charge injection region in a photodiode, once injecting bias charge into the photodiode via the charge injection region, and returning the charge from the photodiode back into the charge injection region through skimming transfer, thereby leaving in the photodiode just an amount of charge which corresponds to the difference between the injected amount and the transferred amount (Sone et al., technical report of the Television Society, ED621, (1982)). There is an example of applying this method to a photoelectric membrane stack type CCD (Japanese Laid-Open Patent Publication No. 2-196575). These method require the additional use of a charge injection region (e.g., an input source) and a control gate (e.g., a skimming control gate TG2), which presents a serious problem concerning the substrate layout of amplification type solid imaging devices which require a high density arrangement of pixels.
Another solution has been proposed which involves the use of a photodiode which is of a complete depletion layer type so that no signal charge is left in the photodiode at the time of reading. This structure requires covering the photodiode surface with a high concentration layer of an opposite polarity, so that a relatively high voltage is required at the time of reading. This detracts from the known advantages of CMOS type image sensors, i.e., low driving voltage, and low consumption power, and therefore cannot be tolerated.